As is well known, flash memory cells are often used for non-volatile storage of data. Large numbers of flash memory cells may be grouped together in an array and provided with associated circuitry to implement a flash memory device. Such flash memory devices may be employed, for example, to store configuration data of a programmable logic device (PLD) such as a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or other device.
Flash memory arrays typically must be erased through a bulk erase operation. In this approach, all flash memory cells of the array are simultaneously provided with appropriate erase voltages which remove stored charges from floating gates of the associated flash memory cells. Unfortunately, this approach does not permit the selective erasing of groups of flash memory cells. As a result, if data values in one group of flash memory cells are to be updated, then all flash memory cells of the array must be erased and reprogrammed. Such processes can be unduly cumbersome to users of flash memory devices.
One approach to providing selective erasing of flash memory cells involves the use of separate flash memory arrays. In this approach, each of the separate flash memory arrays may be bulk erased independently from the others. However, in order to facilitate independent erasure of the arrays, each separate array must be implemented as an independent array with its own associated row driver and bitline decoder circuitry in association with the read and write data paths. This additional circuitry can increase the space required to implement the separate flash memory arrays. In particular, the duplicative bitline decoder and data path circuitry required for each flash memory array can consume significant amounts of integrated circuit area. In many applications, the inefficiencies caused by such space requirements can outweigh benefits gained from the ability to independently erase the separate flash memory arrays.
Accordingly, there is a need for an improved flash memory array structure that provides independently-erasable groups of flash memory cells that overcomes the deficiencies of prior approaches identified above. In particular, for example, there is a need for a flash memory device that provides sector-based erasing without requiring significant integrated circuit area committed to dedicated bitline decoder and data path circuitry.